1. Field of the Invention
The present invention relates to a semiconductor device and a method for testing the same.
2. Related Background Art
The actuation of a semiconductor memory (for example, to read out therefrom or write therein data) requires various potentials. To supply all the potentials from outside, many kinds of external power supplies will be needed. This inevitably calls for a large and complex system that effects the operation of the semiconductor memory. Besides, the necessity for mounting many external power supply terminals on the semiconductor chip increases the chip area and the package size accordingly.
To cope with this, it is customary in the art to supply power from a single power source to the semiconductor chip and generate therein potentials necessary for its operation (which potentials will hereinafter be referred to also as internal potentials). The internal potentials of various levels are each generated based on a potential (hereinafter referred to also as a reference potential) obtained by dividing the potential of the external power supply.
Generally, the reference potential may sometimes deviate from a design value due to stresses applied to the semiconductor wafer during the semiconductor manufacturing process. FIG. 14 is a diagram showing a conventional semiconductor device test procedure. Semiconductor elements formed on the semiconductor wafers in the semiconductor manufacturing process are tested for each die in a D/S (Die/Sort) step. At this time, the reference potential is also measured (S1). If a deviation of the reference potential from the design value is found, the reference potential is trimmed to be close to the design value (S2). This is done by physically cutting a wiring or wirings on the semiconductor wafer through laser irradiation. A description is given below of a conventional reference potential generator for trimming the reference potential.
FIG. 15 is a block diagram of a conventional reference potential generator 500 that generates a reference potential VBGR. Data decision circuits 540-0 to 540-2, which form part of the reference potential generator 500, are each configured as shown in FIG. 16. Each data decision circuit 540 has a fuse 541. Depending on whether or not the fuse 541 in step S2, the data decision circuits 540-0 to 540-2 output high- or low-level 1-bit data as signals SELECT0 to SELECT2.
Referring back to FIG. 15, data transfer circuits 530-0 to 530-2 respectively transfer the signals SELECT0 to SELECT2 to a decode circuit 520. The data transfer circuits 530-0 to 530-2 are also capable of transferring test mode signals TMFUSEDIS to the decode circuit 520 instead of sending thereto the signals SELECT0 to SELECT2.
FIG. 17 shows the configuration of the decode circuit 520, which receives the signals SELECT0 to SELECT2 or TMFUSEDIS as 3-bit digital data composed of signals PRETMBGR0 to PRETMBGR2. Based on the digital data it receives, the decode circuit 520 makes any one of signals TMBGR0 to TMBGR4 high-level and sends it to a reference potential selection circuit 510. FIG. 5 shows the relationships between the signals PRETMBGR0 to PRETMBGR2 and the signals TMBGR0 to TMBGR4. For example, the decode circuit 520 makes the signal TMBGR1 high-level by making the signal PRETMBGR0 low-level and the signals PRETMBGR1 and PRETMBGR2 high-level.
FIG. 18 shows the configuration of the reference potential selection circuit 510, which divides the power supply voltage by resistors R1 and R2 to generate a plurality of different potentials. Based on that one of the signals TMBGR0 to TMBGR4 which is sent thereto, the reference potential selection circuit 510 selects any one of potentials BGR to BGR4, and outputs the selected potential as the reference potential VBGR. For example, when the signal TMBGR1 is high-level, a switch SW1 operates, and the reference potential selection circuit 510 outputs the potential BGR1 as the reference potential VBGR.
In the test mode, the decode circuit 520 receives the test mode signals TMFUSEDIS as digital data, and outputs the signals TMBGR0 to TMBGR4 based on the test mode signals. The reference potential selection circuit 510 responds to the signals TMBGR0 to TMBGR4 to output a preset default potential (hereinafter referred to as a standard potential) as the reference potential VBGR. For example, when the potential BGR2 is the standard potential, the signal TMFUSEDIS is preset so that the reference potential selection circuit 510 selects the potential BGR2.
Referring back to FIG. 14, trimming of the reference potential VBGR in step S2 is followed by a final semiconductor test of the semiconductor wafer (S3), which is thereafter divided into individual semiconductor chips and packaged in an assembling step (S4) and in a packaging step (S5), respectively. Following this, the semiconductor chips undergo a reliability test (S6) and a packaging final test (S7), and are shipped as products.
One possible cause for a semiconductor chip to fail the reliable test (S6) is a deviation of the reference potential VBGR from a design value. The reason for this is that the reference potential VBGR, though adjusted to the design value in step S2, shifts again due to stresses applied to the chip in the reliability test. Since no trimming is possible in the reliable test (S6), however, the semiconductor chip decided as a reject is discarded.
In the D/S step 12, trimming is carried out (S2) on the assumption that the resistors R1 and R2 in FIG. 18 have their design values. Accordingly, the reference potential VBGR does not always become close to the design value, but in some cases it further deviates from the design value.
In the prior art, since the reference potential VBGR measuring step (S1) and the fuse blowing step (2) are separate from each other, an exact value of the trimmed reference potential VBGR cannot be known prior to the fuse blowing step.
To obviate the above-mentioned defects of the prior art, there is a demand for a semiconductor device and its testing method that permits re-trimming or readjustment of the reference potential in the reliability test for each semiconductor chip.
Also, there is a demand for a semiconductor device and its testing method that permits the selection of a reference potential closest to its design value in the test of semiconductor elements for each die and in the adjustment of the reference potential.